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Realizing Multi-Valued Logic Circuits using P-N Heterojunction Electrolyte-Gated Transistors
발표자

한재현 (인하대학교)

연구책임자

이근형 (인하대학교)

공동저자
한재현 (인하대학교), 김리현 (인하대학교), 백승현 (인하대학교), 이근형 (인하대학교)

초록

내용
Multi-valued logic (MVL) offers reduced circuit complexity and lower power consumption compared to binary logic, providing a pathway to higher information density. In this study, we report a ternary inverter circuit composed of an n-type electrolyte-gated transistor (EGT) paired with a heterojunction organic EGT exhibiting negative differential transconductance (NDT). This configuration creates asymmetric carrier injection, resulting in a distinct “N-shaped” transfer characteristic using a high-capacitance ionogel dielectric. We further systematically investigate how the thickness ratio between the p-type and n-type semiconductors modulates the NDT performance. Consequently, the integrated device successfully demonstrates three stable operating regimes, logic ‘0’, ‘1’, and ‘2’, highlighting its potential for high-density, low-power organic logic circuits.

 
발표코드
3PS-066
발표일정
2026-04-10  08:30 - 10:00