제출 정보
권용현 (연세대학교)
조정호 (연세대학교)
초록
This paper presents a reconfigurable binary–ternary transistor featuring a controllable voltage range and current level for the intermediate logic state. The device uses an indium–gallium–zinc-oxide channel with an asymmetric dual-gate structure incorporating high and low capacitance dielectrics.
This design allows the threshold voltage to be tuned via a control gate, while partial depletion makes the off-current dependent on control voltage. By connecting two channels in series, the device produces three current regions: fully depleted (low), partially depleted (intermediate), and accumulated (high). These serve as distinct ternary logic states.
Since the control gates allow for precise biasing, the transistor supports adjustable voltage ranges and seamless reconfiguration between binary and ternary operations. This flexibility makes it a viable candidate for multi-valued logic applications
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