Systematic Study of Solution-Processable Low‐Voltage Carbon Nanotube Transistors (CNTFETs) with High‐k Relaxor Ferroelectric Polymer as Gate Insulator
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Achieving energy-efficient and high-performance FETs is one of the most important goals for future electronic devices. We focused on semiconducting single-walled carbon nanotube (s-SWNT) FETs with high-k relaxor ferroelectric insulator thickness. The s-SWNT-FETs with an optimized thickness of the high-k insulator exhibited the highest mobility of 14.4 cm2V-1s-1 at the drain voltage of 1 V, along with a high current on/off ratio (>105). The optimized device performance resulted from the suppressed leakage current and a large capacitance (> 50 nFcm-2) of insulating layer. The large capacitance and sufficient breakdown voltage of the insulating layer significantly improved p-type performance. On the other hand, a reduced n-type performance was observed owing to the increased electron trap caused by fluorine proportional to the insulator thickness. Hence, precise insulator thickness control is crucial for achieving low-voltage operation with enhanced s-SWNT-FET performance.