Thermal Treatment and Thickness Effects of Polymeric Gate-Insulating Memory Layers in Organic Memory Transistors
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Organic memory devices based on polymers, compared to conventional memory devices with inorganic materials, have received keen attention because of their potential for high flexibility in next-generation electronics systems. In particular, transistor-type organic memory devices (TOMDs) have been extensively studied due to active-control benefit in flexible array modules. However, less attention has relatively been paid to polymeric memory materials, even though various conjugated polymers have been investigated as a channel layer. Our group has recently found that water-soluble polymers are able to deliver good hysteresis characteristics in organic field-effect transistor geometry. Our further investigation demonstrated that the TOMDs with gate-insulating memory layers could be operated at low voltages and exhibited high retention performances. In this presentation, the influence of thermal treatment and thickness for polymeric gate-insulating memory layers will be discussed.