KES5-1454
Development of high-performance p-type Sn perovskite transistors
When and Where
Oct 1, 2026
14:00 - 14:25
Presenter(s)
Yong-Young Noh (POSTECH)
Co-Author(s)
Abstract
Developing high-mobility p-type semiconductors that can be grown using silicon-compatible processes at low temperatures has remained challenging in the electronics community to integrate complementary electronics with the well-developed n-type counterparts [1]. In this presentation, I will introduce high-performance tin (Sn2+) halide perovskite-based p-type transistors using cesium-tin-triiodide-based semiconducting layers[2,3]. The optimized devices exhibit high field-effect hole mobilities of over 50 cm2 V−1 s−1, large current modulation greater than 108, and high operational stability and reproducibility [4]. In addition, we explore triple A-cations of caesium-formamidinium-phenethylammonium to create high-quality cascaded Sn perovskite channel films. As such, the optimized TFTs show record hole mobilities of over 70 cm2 V−1 s−1 and on/off current ratios of over 108, comparable to the commercial low-temperature polysilicon technique level. In the last part, I would like to briefly introduce our recent halide perovskite transistors fabricated by thermal evaporation and how to make an Sn perovskite film stable in air by a volatile coordination reaction [5,6].
- A. Liu, Y.-Y. Noh et al, Nature, 629, 798–802 (2024)
- A. Liu, Y.-Y. Noh et al, Nature Electronics 5, 78-83 (2022)
- H. Zhu, Y.-Y. Noh et al, Nature Electronics 6, 650-657 (2023)
- A. Liu, Y.-Y. Noh et al, Nature Electronics 6, 559-571 (2023)
- Y. Reo, Y.-Y. Noh et al, Nature Electronics 8, 403-410 (2025)
- G. Park, Y-Y. Noh et al, 655, 357-363 (2026)
