Self-Aligned Sol–Gel Metal Oxide Heterojunction Transistors for Scalable Multivalued Logic Devices

The rapid growth of digital information density has driven increasing interest in multi-valued logic (MVL) systems, which can reduce computational complexity, energy consumption and processing time. Heterojunction transistors provide a promising platform for MVL circuits; however, the fabrication of partially overlapped heterostructures has largely been limited to vacuum-deposited organic semiconductors and transferred two-dimensional materials owing to patterning constraints. Here, we demonstrate a ternary inverter based on a partially overlapped Cu_xO/IGZO heterojunction fabricated through a sol–gel process and direct patterning using a self-assembled monolayer (SAM). This method provides a simple alternative to conventional photolithography while preserving the electrical characteristics of the oxide thin-film transistors relative to those of unpatterned reference devices. Structural characterization confirms the formation of a smooth, partially overlapped heterojunction interface. Depth-resolved X-ray photoelectron spectroscopy further reveals an oxidation-state gradient within the Cu_xO layer, indicating an increased Cu⁺ fraction near the IGZO interface. This interfacial modulation facilitates hole transport and gives rise to negative differential transconductance, enabling stable ternary logic operation. These results establish a scalable and cost-effective route toward large-area, solution-processed MVL electronics.