ORGS4-1197
Suppressing Hysteresis in Vapor-Deposited Tin Perovskite Transistors via Additive Engineering
Topic
GS4. Graduate Student Oral Session IV: Polymers for Electronics, Photonics, and Energy
When and Where
Sep 28, 2026
15:36 - 15:48
Room 104
Session Chairs
Hobeom KIM
Giwon LEE
Hyeong Jun KIM
Presenter(s)
Hyeyeon Jung (POSTECH)
Co-Author(s)
Abstract
Tin halide perovskites are attractive lead-free p-type semiconductors for thin-film transistors (TFTs), yet their device performance is limited by severe self p-doping and pronounced hysteresis. Here, we demonstrate that incorporating CdCl2 effectively addresses both challenges, yielding p-type TFTs with an on/off current ratio of ~106 and minimized hysteresis. Cd2+ and Cl- concurrently fill Sn and I vacancies, respectively, passivating the excess hole density arising from Sn vacancies and suppressing the voltage bias-induced ion migration responsible for hysteresis. This vacancy filling also enhances the structural resilience of the film, reinforcing its resistance to oxidation. In addition, the additive lowers the thermal activation barrier for complete perovskite phase transition, enabling solid-state CsSnI3 formation at reduced temperatures. These findings establish additive engineering as an effective strategy for regulating vacancy chemistry, suppressing ion migration, and reducing the thermal budget of vapor-deposited tin halide perovskite films, offering a practical route toward stable and industry-compatible manufacturing of perovskite electronics.
