POS5-1067
Back-End-of-Line compatible wafer-scale InSe transistors
When and Where
Nov 30, -0001
00:00 - 00:00
Presenter(s)
JAEYUN LEE (POSTECH)
Co-Author(s)
Abstract
Two-dimensional (2D) semiconductors are regarded as promising materials for next-generation electronics beyond silicon due to their atomically thin structures and excellent electrostatic control. Among them, indium selenide (InSe) offers exceptionally high carrier transport properties originating from its small electron effective mass. However, most InSe devices reported to date rely on relatively thick channels (>10 nm) and suffer from scalability issues in film synthesis. In this work, we demonstrate wafer-scale fabrication of ultrathin crystalline β-InSe films via a facile thermal evaporation and post-annealing process conducted under back-end-of-line (BEOL) compatible conditions (< 450 °C). The fabricated devices operate reliably even at an ultrathin thickness of 1.8 nm, where efficient percolation pathways are maintained across the channel. Notably, transistors with a 4.5 nm InSe channel exhibit optimal electrical characteristics, achieving the best trade-off among mobility, on/off ratio, threshold voltage, and carrier concentration. Furthermore, integration of a 24 × 24 transistor array (576 devices) on a 4-inch wafer demonstrates uniform performance, with an average mobility of 40.3 cm2 V−1 s−1 and narrow distributions of threshold voltage and subthreshold swing. Such findings position thermally evaporated InSe semiconductor as a scalable and BEOL-compatible material platform, paving the way for high-performance, ultrathin electronics.
