POS5-0965
Leakage-Suppressed Polymer FeFETs via Nanowire Patterning for High-Precision Artificial Synapses
When and Where
Nov 30, -0001
00:00 - 00:00
Presenter(s)
USEONG JIN (Korea maritime of ocean university)
Co-Author(s)
Abstract
Organic ferroelectric gate dielectrics offer distinct advantages such as low-cost solution processability, fatigue-free remnant polarization, and tunable polarization magnitude, enabling reliable non-volatile operation. These features have attracted considerable attention for high-performance memory and neuromorphic synaptic devices. However, the high leakage current originating from ferroelectric insulating layers can degrade electrical performance and memory retention, limiting device reliability. Therefore, minimizing leakage current is essential for stable and reliable operation across various applications.
In this study, we introduced a nanowire patterning technique using a soft master mold to fabricate polymer-based ferroelectric field-effect transistors (FeFETs). Compared to conventional spin-coated devices, the nanowire-patterned FeFETs exhibited reduced off-state leakage and an expanded memory window, owing to well-established charge transport pathways within the nanowire architecture that suppress leakage and promote efficient carrier conduction. The nanowire-structured ferroelectric layer also enabled stable charge retention and programmable memory characteristics. Through ferroelectric polarization switching, the devices realized multi-level memory behaviors and emulated synaptic plasticity, showing multi-bit and synaptic weight modulation with gradual, controllable conductance variation under repeated stimuli. By combining low leakage with multi-level functionality, these polymer FeFETs offer a reliable, energy-efficient platform with strong potential for high-precision synaptic applications.
Acknowledge
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (RS2022NR071808) and partially supported by Korea Basic Science Institute (National research Facilities and Equipment Center) grant funded by Ministry of Education (grant No. 2022R1A6C101B738)
In this study, we introduced a nanowire patterning technique using a soft master mold to fabricate polymer-based ferroelectric field-effect transistors (FeFETs). Compared to conventional spin-coated devices, the nanowire-patterned FeFETs exhibited reduced off-state leakage and an expanded memory window, owing to well-established charge transport pathways within the nanowire architecture that suppress leakage and promote efficient carrier conduction. The nanowire-structured ferroelectric layer also enabled stable charge retention and programmable memory characteristics. Through ferroelectric polarization switching, the devices realized multi-level memory behaviors and emulated synaptic plasticity, showing multi-bit and synaptic weight modulation with gradual, controllable conductance variation under repeated stimuli. By combining low leakage with multi-level functionality, these polymer FeFETs offer a reliable, energy-efficient platform with strong potential for high-precision synaptic applications.
Acknowledge
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (RS2022NR071808) and partially supported by Korea Basic Science Institute (National research Facilities and Equipment Center) grant funded by Ministry of Education (grant No. 2022R1A6C101B738)
