POS5-0957
Vertically Integrated Conjugated Polymer Transistors for Monolithic 3D CMOS Inverters
When and Where
Nov 30, -0001
00:00 - 00:00
Presenter(s)
SangHwa Song (Korea Maritime and Ocean University)
Co-Author(s)
Abstract
To increase the integration density of electronic devices, 3D vertical stacking of transistors is gaining attention. In vertically stacked devices, Parylene C is frequently employed as a gate dielectric and interlayer material due to its chemical stability, capability for uniform conformal deposition. [1] However, Parylene C has a low dielectric constant and a rough surface, which can cause poor interfacial contact and lead to reduced charge transport and overall device performance. [2]
In this study, we demonstrate vertically stacked thin-film transistors based on semiconducting conjugated polymers, using nanowire alignment to enhance electrical performance. The device is constructed by vertically stacking a p-type transistor over an n-type transistor, both operating under a shared gate configuration. A nanowire patterning technique using a master mold was applied to induce polymer chain alignment, which significantly enhanced electrical properties such as mobility, subthreshold swing (SS), and the on/off current ratio. Using this structure, we fabricated a 3D inverter, and the results of the analysis showed full output voltage swing and high voltage gain. This work offers a promising route toward high-density vertically integrated polymer electronics with enhanced performance and circuit-level functionality, contributing to next-generation compact organic logic circuits and integrated systems.
Acknowledgments
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (RS2022NR071808) and partially supported by Korea Basic Science Institute (National research Facilities and Equipment Center) grant funded by Ministry of Education (grant No. 2022R1A6C101B738)
References:
In this study, we demonstrate vertically stacked thin-film transistors based on semiconducting conjugated polymers, using nanowire alignment to enhance electrical performance. The device is constructed by vertically stacking a p-type transistor over an n-type transistor, both operating under a shared gate configuration. A nanowire patterning technique using a master mold was applied to induce polymer chain alignment, which significantly enhanced electrical properties such as mobility, subthreshold swing (SS), and the on/off current ratio. Using this structure, we fabricated a 3D inverter, and the results of the analysis showed full output voltage swing and high voltage gain. This work offers a promising route toward high-density vertically integrated polymer electronics with enhanced performance and circuit-level functionality, contributing to next-generation compact organic logic circuits and integrated systems.
Acknowledgments
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (RS2022NR071808) and partially supported by Korea Basic Science Institute (National research Facilities and Equipment Center) grant funded by Ministry of Education (grant No. 2022R1A6C101B738)
References:
- S. Kim, J. Seo, J. Choi, H. Yoo, Nanomicro Lett 14 (2022) 201.
- S. Sang, L. Li, Q. Li, L. Ding, X. Li, Z. Chang, Y. Chen, R. Ullan, J. Ma, J. Ji, iScience 27 (2024) 109724.
