Multi-threshold Transistors based on Self-Stratified Heterojunctions
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초록
내용
Recent semiconductor market surrounding AI compels new electronic technology to accommodate its rapid growth. However, Moore’s Law is currently facing an enormous challenge in further scale-down of chips. Multi-value logic (MVL) has thus emerged as an alternative, which still has future avenues to explore – reducing device footprint and simplifying fabrication process. To this end, we suggest a new device architecture for multi-threshold transistors based on vertically self-stratified organic heterostructures. This involves independently controlling threshold voltages of each material via engineering heterointerface structures, which aims at sequentially, stably and equiprobably accessing different “ON” states of each material. To facilitate vertical self-stratification, organic materials with chemically finely tuned miscibility and energy levels are adopted. The possibility of multi-threshold voltage device to be implemented in conventional CMOS system was further studied.