Well-balanced Hole and Electron Charge Transport in an Organic P-type-Insulator-N-type Layered Sandwich Structure
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The robust operation of p/n stacked ambipolar transistors relies on maintaining a harmonious current flow of both holes and electrons, a balance pivotal for optimizing performance across various applications. To achieve this equilibrium, our research proposes the integration of a thin layer of parylene between the p/n junctions. This layer is designed to augment reinforced hole current in p/n stacked ambipolar transistors by improving the surface of DNTT. In the case of the PTCDI-C13/parylene/DNTT (PPD) transistor, our investigation reveals a balanced polarity ratio of 1.08:1 at VDS = -20 V. In addition, we investigated the realization of a complementary-like inverter utilizing a PPD transistor as a pull-up device and a PTCDI-C13/DNTT (PD) transistor as a pull-down transistor. This configuration demonstrated enhanced noise margins and stable pull-up and pull-down operations, even under transient pulse measurements.