Wafer-Scale Logic Circuits Based on Vertically Stacked CVD-Grown Graphene/MoS<SUB>2</SUB> Heterostructure
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This paper demonstrates, wafer-scale graphene/MoS2 heterostructures prepared by chemical vapor deposition (CVD) and their application in vertical transistors. A CVD-grown bulk MoS2 layer is utilized as the vertical channel, whereas CVD-grown monolayer graphene is used as the tunable-work-function electrode. The electron injection barriers at the graphene-MoS2 junction and ITO-MoS2 junction are modulated effectively through variation of the Schottky barrier height and its effective barrier width, respectively, because of the work-function tunability of the graphene electrode. The resulting vertical transistor with the CVD-grown MoS2/graphene heterostructure exhibits excellent electrical performances, including a high current density exceeding 7 A/cm2, a subthreshold swing of 410 mV/dec, and a high on-off current ratio exceeding 103.